By industry convention, flash memory devices are typically categorized as NAND or NOR flash memory, based on the underlying circuit technology used in the memory arrays. Due to the inherent characteristics of each, NOR flash is typically used for truly random access applications in which single addresses are frequently read/written (e.g., as with instruction code), while NAND is typically used for block-oriented applications in which entire blocks of data are read or written together (e.g., as with digitized graphics images). Conventional NAND flash memory uses an asynchronous control interface that relies on a number of control signals for reading and writing data. For example, separate control signals such as Address Latch Enable (ALE), Command Latch Enable (CLE), and Read Enable (RE) may each be implemented on separate pins to trigger the associated functions. However, as pressure increases to reduce both the cost and size of the NAND flash chips, the cost of installing those additional pins, and the size limits imposed by them, become factors that limit increased use of NAND flash.